Despite the advent and popularity of specialized computation models such as machine learning, near-memory computing or neuromorphic computing, general purpose computing remains ubiquitous in systems, whether embedded or high performance. Therefore, performance, energy-efficiency, reliability, and resisting to information leakage remains of great importance.
CocoRISCo aims to advance state-of-the-art on these topics by leveraging the opportunity brought by the RISC-V instruction set: its extensibility. This allows modifying the hardware-software interface to improve, e.g., performance by working on several layers of computing system stack. For instance, the instruction set can expose a finer interface to the memory hierarchy and the coherency protocol to software, so that it can convey to hardware algorithm-level information that will reduce the traffic on the network on chip. Similarly, control flow security primitives can be added to the instruction set in order to allow software to specify which data must be isolated within the hardware.
The choice of RISC-V is significant and can be explained by the fact that although possible, modifying existing proprietary instructions sets (e.g., x86, ARM) is nigh impossible if the proposal comes from a third party. Moreover, the rise of RISC-V has led to the emergence of a whole ecosystem of academic and industrial contributors to opensource hardware, whether processors or more specific functions such as caches or peripherals. Making a significant contribution to improving existing opensource hardware is a priority for CocoRISCo, as is the production of hardware and software demonstrators.