Opensource
RISC-V open-source microprocessor: what are the opportunities for software engineering and security research?
Date:
Changed on 19/10/2022
Presented as the most promising of its generation, the RISC-V microprocessor opens up a wide range of opportunities for the international software engineering and hardware community. It is easy to see why: this microprocessor, created by the University of Berkeley in 2010 and available in a stable version since 2017, offers developers an open architecture system. The Ensta Bretagne/Inria centre at the University of Lille collaboration is bearing fruit with the RISC-V just-in-time (JIT) compilation for Pharo.
Main part and brain of the computer
The central component and brain of any computer, the microprocessor is the essential computational element that allows it to execute instruction sets, i.e., a given program, called an Instruction Set Architecture (ISA). User applications are translated into this low-level language using a translator (the compiler). Most processors on the market today are made by hardware giants and have closed architectures. Developers wanting to use specific instructions or elements of the platform must comply with the restrictions imposed by the manufacturer. This model leaves little room for initiatives to extend these architectures that do not come from the manufacturers themselves.
Thanks to its open-source model, RISC-V removes these barriers. The instruction set and various processor models are open-source and their implementation is maintained and monitored by companies or consortia who support the initiative. Thalès, for example, a member of the Open Hardware Group bringing together industrial actors and universities, maintains the CVA6 processor. Access to the implementation of these processors and tools allows users to extend a processor to support new dedicated instructions (e.g., dedicated instructions for artificial intelligence) or add dedicated modules to it (e.g., a safety monitor). For Loïc Lagadec, a Professor at Esta Bretagne, Lab-STICC UMR CNRS 6285:
This possibility opens perspectives for research and industry in a very broad range of applications, from the smallest microcontrollers (IoT) to high-performance computing (HPC).
Aware of the potential offered by this type of processor, NASA has announced its intention to equip all future space modules with RISC-V. All over the world, numerous initiatives are being launched to implement virtual machines (a virtual machine is an “illusion” of a physical computer system) using this instruction set.
A successful collaboration between two teams
In France, the Arcad team at ENSTA Bretagne has extended a JIT compiler using RISC-V for the Pharo programming language. A JIT compiler generates low-level programs in machine language that can be directly run on a microprocessor (in this case RISC-V) while the program expressed in a high-level language (Pharo) is running. The JIT compiler is representative of modern architectures in JavaScript, Java, C#, etc.
This achievement is the fruit of collaboration between the Arcad team at ENSTA Bretagne, which specializes in the design and validation of microprocessors, and the RMOD* project team, which produces the Pharo language and its virtual machine. Quentin Ducasse, a Ph.D. student in the Arcad team, has extended the virtual machine to obtain one of the very first JIT RISC-Vs.
Having RISC-V support for Pharo opens up new possibilities for instruction set extensions, such as securing a virtual machine, designing dedicated virtual machines, deploying software/hardware solutions, and specific optimizations.
* RMOD is a project team common to Inria and the University of Lille