Whether it’s in aeronautics, the automotive industry, telecommunications or the internet of things - over the past twenty years, embedded systems have spread rapidly, and are now used for a wide range of tasks. But designers and users are always hungry for more. This appetite has hit a stumbling block, however, in the form of the limited amount of energy available for powering processors. As a result, it has become necessary to optimise not just the material aspect of these chips, but the applications using them as well. This is exactly what Justine Bonnot has been working on. She recently completed a PhD in Rennes at the IETR/Insa laboratory.
The Institut d'Électronique et de Télécommunications de Rennes (IETR) is a mixed unit (UMR 6164) bringing together research teams from INSA Rennes, the University of Rennes 1, Centralesupélec, the University of Nantes and the CNRS.
The subject of her PhD was approximate computing which involves “easing the level of precision for calculations in order to be able to operate using an architecture that consumes less energy.” In other words “intentionally cutting back on the output quality of the embedded application in order to make it more energy efficient.” But does that not create issues? “No, provided we manage to strike the right balance. You have to find an acceptable level of downgrading that will enable you to save energy.”
And not just a little. “Decreasing the number of bits used in processing reduces the amount of electricity used quadratically”, explains Olivier Sentieys, who heads up Cairn, an Inria (2) team specialising in research into frugal architecture. “The goal is to switch from code C, which uses a floating point, to specification, which uses fixed point arithmetic. If you can manage to convert 64 bits with a floating point into 12 bits with a fixed point, for example, then you can really make huge gains.” In order to achieve this, the researchers working within Cairn designed TypEx, a prototype compiler that takes an application’s existing code and optimises it in accordance with the quality/performance compromise set by the developer.
Cairn is a research team Inria, ENS Rennes, Université Rennes 1, CNRS, common to Irisa (UMR CNRS 6074).
Exploring a range of solutions
In practise, “the tool will explore a design field. Within this field, it will determine a range of possible compromises, selecting the most appropriate for what is being requested. This compromise must deliver in excess of the desired quality levels but at the lowest possible cost. This might relate to energy, its memory footprint or the amount of silicon taken up. Until recently, this tool took hours to complete its exploration - now, thanks to the work carried out by Justine as part of her PhD, the time taken has been massively reduced. Contributions have also been made by Inria researcher Tomofumi Yuki and PhD student Van-Phu Ha, helping to reduce the complexity of exploration. Their approach involved breaking complex applications down into different cores and using methods from machine learning in order to combine local optimisations.”
This improvement comes at a time when “a number of the team’s tools have achieved a certain degree of maturity”, giving them the idea to set up a company in order to provide them to industry. After completing her PhD (3), Justine Bonnot is now set to join Inria’s start-up incubator in order to help this project - which she will be responsible for running - to mature. “Inria is also funding the cost of an engineer for 12 months, and we will be supported by the Insa Rennes and the technology transfer acceleration company Ouest Valorisation, which is funding market research and which helped us when it came to filing a patent.”
FPGA
Which field is this new tool targeting? “More towards material accelerators based on FPGA, where the level of precision can be adjusted, as well as embedded processors”, answers Olivier Sentieys. “Currently, there is no software as generic as ours in the CAD sector.” Manual optimisation efforts, meanwhile, remain extremely time-consuming. “Switching from floating point 64 bit in MatLab on a PC to an FPGA or an embedded processor with no floating unit takes a long time. It can take up as much as 50% of the implementation time, with a whole host of engineers required. Switching to a reduced level of precision remains a critical step when it comes to designing embedded systems.”
The plan is for the prototype to be manufactured over the next 18 months. “We also want to come up with a design brief that will enable us to stick as closely as possible to the needs of companies”, adds Justine Bonnot. “While studying for my PhD, I interviewed some fifteen or so manufacturers faced with these sorts of problems in order to gauge expectations.”
Interested by real-life examples
Before the software is made available on the market, the start-up will use it internally in order to offer services. “During this initial phase, we will be looking for manufacturers keen to entrust us with optimising applications that are giving them difficulties. This will give us the opportunity to try out our tools on real industrial applications.”
