André Seznec - microprocessor architect

André Seznec began his career in Rennes in 1983, where he still lives and works today. But far beyond Brittany, the wealth of research he has carried out on microprocessor architecture and microarchitecture has earned him recognition as one of the world's leading researchers in this field. In 2010, for instance, he received a five-year ERC Advanced Grant, while in 2012 he won the first Intel Research Impact Medal. In 2013 and 2016 he was made an IEEE Fellow as well as an ACM Fellow, and in 2020 he won the B. Ramakrishna Rau Award from the IEEE.

André Seznec took a leave of absence from his position as a permanent researcher with Inria in early 2021 and is currently carrying out research for Intel.

André Seznec developed an interest in processor architecture very early on in his career. As these components have developed and been miniaturised, tasked with executing instructions from computers and processing programme data, his research has continued to progress. The 1990s and 2000s were “a golden age for the discipline, a time where we saw an explosion in the number of transistors in microprocessors”, explains the researcher. He started by doing a thesis on “highly pipelined multiprocessors” supervised by Jacques Lenfant, would go on to become president of the University of Rennes 1.

“Multiprocessors were the forerunners to the multicore processors we have today”, explains André Seznec. “Back then, processors took up large printed circuit boards measuring 60-80 cm by 50-60 cm. Memory was stored on other circuit boards, and multiprocessors were comprised of around a dozen or possibly more high performance processors.” He adds that “pipelines” involved “dividing instructions into N number of steps in order to simultaneously execute N instructions, each contained within a single step.”  This helped to speed up processing: “It was no longer necessary to wait for an instruction to be executed before launching the next one.” 

Upon completion of his PhD, André Seznec became an Inria researcher at the Irisa (a joint laboratory involving a number of institutions, including Inria, CNRS and universities) in Rennes. He designs and builds a prototype of a matrix computing gas pedal. “This really helped me later on in my career as a researcher. In the 1990s, my attentions turned towards microprocessor architecture. By then it was possible to fit an entire high performance processor onto a single component measuring 2 to 3 cm², and before long much of the memory hierarchy as well. I grew familiar with the design of processors.” 

André Seznec went on to develop cache memory architecture (the part of the memory where data is temporarily stored in order to speed up processing) and branch predictor mechanisms (used to predict which way a branch will go in order to optimise use of pipelines). He never lost interest in these two subjects.

I carved a niche for myself in those two fields of research, which is where I’ve received the majority of the distinctions I’ve been awarded. I also knocked on doors so that I could present my research to the main microprocessor manufacturers: Intel, ARM, AMD, IBM, Motorola, Qualcomm, Sun Microsystems, and so on. This gave me the chance to share ideas with them and to make suggestions as to possible developments.

1994 was another pivotal year for André Seznec. It was then that he founded the project team CAPS (“Compilateur, architecture parallèle et systèmes” - Compiler, Parallel Architecture and Systems), which he would lead until 2008, before taking charge of the project team ALF in 2009.

The mechanisms we developed inspired a number of processor manufacturers

In 1999 André Seznec took a sabbatical to work at the American laboratories of the manufacturer Compaq (later taken over by Hewlett Packard). “I helped to design their Alpha EV8 processor, contributing to the specifications. It was to be the fastest processor for the period 2002-2005. Unfortunately the project wasn’t completed, but we were able to share the design of the branch predictor with the scientific community, and it remains a reference point to this day.” 

In the mid-2000s André Seznec created TAGE, which is still considered the pinnacle of branch predictors. He chose to hand over the reins of his team in 2016 - “To give someone younger a chance!” – and ALF was replaced by PACAP (which stands for “Performance des applications par la compilation et l'architecture des processeurs” - The Performance of Applications by Compilation and Processor Architecture). This project team, which André Seznec was a member of until 2020, was set up to improve “the performance of computers”, i.e. “the speed programmes are executed at.” The race for the best architecture continues.

• For beginners: Memory and mainframe, a couple focused on executing programmes, Interstices, 21/6/2019.
• The processor that speculated more than a trader, by Arthur Perais, Binaire, 22/2/2017. “The most remarkable contribution made by the ALF project team with ERC funding”, explains André Seznec.
• The multi-core processors of today and tomorrow, Interstices podcast, 28/1/2011
• PER-18: André Seznec on effective value prediction implementation, HiPEAC TV, 30/5/2018.
• André Seznec and Daniel A. Jimenez, “Branch Prediction: Jim, Yale, André, Daniel and the others”, Yale: 80 in 2019, 1/7/2019.